We will most likely see the L2 cache size problem addressed in Westmere. AnandTech published an article where Intel recognized that the current cache situation is not ideal. A larger L2 size on the current process is hard to justify because that would decrease the effective size of the L3 cache, due to its inclusiveness as Mastergee pointed out. A larger L2 would have to come with a larger L3, which can be made possible with the extra transistors in 32 nm.

What would be interesting is that if HT for Rosetta is limited due to the shared use of the FPU, then would there be less of a performance drop when running an integer-heavy BOINC project on the other logical core. If this were true, then the ideal case is for BOINC or the OS to set process affinity such that each physical CPU runs an ideal mix of work.

8 children + cookies = no cookies

Funny!

My point was simply that "it depends". ...if the kitchen is large enough, it can work more efficiently. But even if floor space (L2 cache) is not the problem, other key resources such as mixing bowel (bus), and oven (math coprocessor) may become bottlenecks.

Just think of it as 2/3 + 2/3 = 4/3. So even if each "hyperthreaded" core is only 2/3 as powerful as a full core

You can also think of it as a 10 year old being 2/3rds of a baker... now picture 8 of them in your kitchen and what will happen to your cookies? Faster? or slower?

Either outcome is possible. Time will tell.

I have downloaded this application but cannot seem to install it on my phone, how do we do this? I have a Sony Ericsson W850i

The developers have re-released the code using CVS, you should look at the SF page for details.
The code, though, is written in Java SE, so it will need to be converted to Java ME to run on your mobile phone (I'm testing on a Sony Ericsson K610i), but I have not yet been successful.

I certainly haven't given up though, there's at least three Sony Ericsson phones here that could be crunching WUs. :-)

Only SETI has been ported to Java at the moment anyway, you would need to obtain the source code, and port it manually, for each product if it is available for download.

Remember: the code is pre-alpha, moving WUs around needs to be done manually also.

A X2 2.8ghz AMD only has a 2mb processor cache, the E8400 has a 6 mb processor cache. The bigger the processor cache, the more credit you are granted, especially for work units that are cache sensitive, like the Rosetta mini. The Intel core 2 Duo's are the way to go for building a crunching machine, and they use much less power and electricity than an AMD.

... and which directory is it located in ?

(I assume its value is in seconds, not hours)

Thanx!

Is your memory voltage set correctly, what memory is it (512MB stick of 400MHz DDR PC3200) but what exactly is it , Corsair , OCZ , Crucial etc. A part number would be good and also to know what your BIOS memory voltage is set to.

Had similar problems when memory voltage was set -0.2V below spec of OCZ DDR2 DIMM - PC would run but give it anything "heavy" to do and ...... POP ! BSOD or lock up