80 cores, not science fiction ... it is real! 1.2 TERA!

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Message 36638 - Posted: 13 Feb 2007, 6:34:27 UTC


TERA SCALE!!!


So, many people asked me details about the 80 cores demo wafer, here is more public information.

For those who think it is science fiction (Matt ;-)
here is some nice "real" stuffs ...

if it is science fiction: "beam me up Scotty!"

energize!

who?
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zombie67 [MM]
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Message 36645 - Posted: 13 Feb 2007, 7:59:27 UTC - in response to Message 36638.  


TERA SCALE!!!


So, many people asked me details about the 80 cores demo wafer, here is more public information.

For those who think it is science fiction (Matt ;-)
here is some nice "real" stuffs ...

if it is science fiction: "beam me up Scotty!"

energize!

who?


Yeah, but will it run Win98? =;^)
Reno, NV
Team: SETI.USA
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Michael.L

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Message 36652 - Posted: 13 Feb 2007, 10:07:14 UTC

there is a fairly long article on BBC news {internet} today about 80 core, so it must be official!! Tried to copy/paste.
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The_Bad_Penguin
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Message 36655 - Posted: 13 Feb 2007, 13:18:29 UTC - in response to Message 36638.  

To follow up on zombie67's thoughts:

Are these 80 "cores" in the same sense as the current quad cores? i.e., will an os task manager show 80 individual cores, each capable of running a distinct instance of boinc/rosetta?

From what I've read so far, these are not x86 cores, though there are claims that they could be in the near future.

"Assuming" this is true, the question remains, are/will these (be) "real" x86 cores as defined currently? Will I be able to run 80 instances of Rosetta?

So, many people asked me details about the 80 cores demo wafer, here is more public information.

who?
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Message 36752 - Posted: 13 Feb 2007, 16:48:33 UTC - in response to Message 36655.  
Last modified: 13 Feb 2007, 16:49:45 UTC

To follow up on zombie67's thoughts:

Are these 80 "cores" in the same sense as the current quad cores? i.e., will an os task manager show 80 individual cores, each capable of running a distinct instance of boinc/rosetta?


Not exactly... It's closer to a BeoWulf cluster on a chip... It probably will run 'embarrassingly parallel' applications, to which BOINC does qualify...


From what I've read so far, these are not x86 cores, though there are claims that they could be in the near future.

"Assuming" this is true, the question remains, are/will these (be) "real" x86 cores as defined currently? Will I be able to run 80 instances of Rosetta?

So, many people asked me details about the 80 cores demo wafer, here is more public information.

who?


They would be insane not to use the x86 technology, which they have so much time invested.. Engineers love new things and they love to change things.... but they are also pragmatic enough to hate breaking things... I would bet the farm on x86 or enhanced x86 compatibility... probably of the x86_64 variety tho...


Looking for a team ??? Join BoincSynergy!!


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Message 36753 - Posted: 13 Feb 2007, 17:45:03 UTC - in response to Message 36655.  
Last modified: 13 Feb 2007, 17:45:27 UTC

More information and video:

Web page of Intel research Lab

the video ... it is running!


guys, this is the intel research web page, i can t add anything on the top.
enjoy the video, from a building floor to a single chip.

I am proud of working for this company!

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Message 36754 - Posted: 13 Feb 2007, 17:46:59 UTC
Last modified: 13 Feb 2007, 17:51:58 UTC

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Message 36755 - Posted: 13 Feb 2007, 17:54:15 UTC - in response to Message 36754.  
Last modified: 13 Feb 2007, 17:56:53 UTC

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Message 36756 - Posted: 13 Feb 2007, 18:00:33 UTC - in response to Message 36755.  

And what about this... http://www.dwavesys.com/index.php?mact=News,cntnt01,detail,0&cntnt01articleid=4&cntnt01origid=15&cntnt01returnid=21

http://www.dwavesys.com/index.php?page=bioinformatics


http://www.dwavesys.com/index.php?page=quantum-computing


The presentation is/was today...


nice :)
but did not compute anything yet ...

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Do you have any news about this? I can't find anywhere nothing about the presentation. I'm really curious to know if that's real and if the results are so good as they say. Until know it's all teoric, I'm hopping to see something real.
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Message 36757 - Posted: 13 Feb 2007, 20:07:42 UTC - in response to Message 36754.  
Last modified: 13 Feb 2007, 20:08:48 UTC

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Message 36830 - Posted: 15 Feb 2007, 9:48:21 UTC

Coming back from the quantum world to the Intel 80 core chip, is this a prototype design only, or has it actually been built and powered up and run?

The biggest issue for chips like this is getting terabytes of data into them at the start of a program, and out again at the end.

On the other hand, an application like Rosetta is ideal. Rosetta loads a comparatively small date set at startup, then runs many different 'decoys' on the same data. In current versions of Rosetta, these are run sequentially, but it would not be hard for programmers to add a facility to make the program start 80 threads at once, all with the same data and each with a separate random number seed.

With such a dedicated app, the small amount of data would need to be loaded onto the chip at the outset, and then replicated within the chip taking advantage of the high speed shared caches and fast bandwidth. Even mesh architecture for comms between cores is no problem when each core neeed the same data - each core would read, keep, and pass on. The outlying chips would be a few comms cycles behind the nearby chips in getting started, but that is all.

For Rosetta, all that needs to be reported back is the best decoy and the number of decoys run. As with the input, only one set of data out to the 'slow' front-side bus.

With dedicated hardware and a re-written Rosetta, recompiled for the very basic chip that has been currently designed, Rosetta would run 80x faster than on a single core device wiuth the simple instruction set. And Rosetta uses only single precision maths, just does a lot of it. Reduced instruction set is not going to hurt Rosetta performance as much as it would (say) SETI or Einstein with their massive FFTs and so on.

Now to my point: Intel are never likely to market such a chip, the finance numbers say they need a mass market where there is also a much faster front side bus, RAM, disks, etc. Ordinary users (ie not BOINC-heads) will not buy a terachip unless they can also do the next generation of killer apps.

But, wouldn't Rosetta be a good prototype app to showcase the uses of the chip without needing the rest of the hardware to be tera-scale? If Intel have got as far as actually producing this chip and a motherboard with ordinary RAM and so on, why don't they throw Rosetta at it?

Rosetta would show up on-chip problems at an early stage (excessive heating etc) and when it worked (as it would after the engineers had worked round the inevitable issues) then what the IT engineers think is demo data would be what David et al think of as useful results.

Just a thought... At one time Microsoft was the top team on SETI. We could see an Intel team become the top team on Rosetta, and certainly with a chip like that they'd easily get the best host.

River~~
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Message 36849 - Posted: 15 Feb 2007, 17:57:03 UTC - in response to Message 36830.  

Coming back from the quantum world to the Intel 80 core chip, is this a prototype design only, or has it actually been built and powered up and run?

The biggest issue for chips like this is getting terabytes of data into them at the start of a program, and out again at the end.

On the other hand, an application like Rosetta is ideal. Rosetta loads a comparatively small date set at startup, then runs many different 'decoys' on the same data. In current versions of Rosetta, these are run sequentially, but it would not be hard for programmers to add a facility to make the program start 80 threads at once, all with the same data and each with a separate random number seed.

With such a dedicated app, the small amount of data would need to be loaded onto the chip at the outset, and then replicated within the chip taking advantage of the high speed shared caches and fast bandwidth. Even mesh architecture for comms between cores is no problem when each core neeed the same data - each core would read, keep, and pass on. The outlying chips would be a few comms cycles behind the nearby chips in getting started, but that is all.

For Rosetta, all that needs to be reported back is the best decoy and the number of decoys run. As with the input, only one set of data out to the 'slow' front-side bus.

With dedicated hardware and a re-written Rosetta, recompiled for the very basic chip that has been currently designed, Rosetta would run 80x faster than on a single core device wiuth the simple instruction set. And Rosetta uses only single precision maths, just does a lot of it. Reduced instruction set is not going to hurt Rosetta performance as much as it would (say) SETI or Einstein with their massive FFTs and so on.

Now to my point: Intel are never likely to market such a chip, the finance numbers say they need a mass market where there is also a much faster front side bus, RAM, disks, etc. Ordinary users (ie not BOINC-heads) will not buy a terachip unless they can also do the next generation of killer apps.

But, wouldn't Rosetta be a good prototype app to showcase the uses of the chip without needing the rest of the hardware to be tera-scale? If Intel have got as far as actually producing this chip and a motherboard with ordinary RAM and so on, why don't they throw Rosetta at it?

Rosetta would show up on-chip problems at an early stage (excessive heating etc) and when it worked (as it would after the engineers had worked round the inevitable issues) then what the IT engineers think is demo data would be what David et al think of as useful results.

Just a thought... At one time Microsoft was the top team on SETI. We could see an Intel team become the top team on Rosetta, and certainly with a chip like that they'd easily get the best host.

River~~


look at the video link below, it is working, really working, my employeer would not tell that is the goal of the experimentation yet, but it is obviously working well. The stackable packaging will allow them the get the RAM close to the cores, and if you look at the optical link intel has ... put that together, and you have the baby of our CEO: the Tera Scale!
We are all behing it, this is a real break through, as the High K silicon process is.

we are all working very hard, and we are having fun with our new toys! Can t wait to see the productization of all those great discoveries.


who?
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Message 37639 - Posted: 9 Mar 2007, 14:59:13 UTC - in response to Message 36849.  

Can t wait to see the productization of all those great discoveries.


I imagine it will be a long time before average Joe's can consider owning something like this. We need to buy our way through the current chips so Intel can make as much money as possible off all of this.
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Message 37699 - Posted: 12 Mar 2007, 8:29:55 UTC - in response to Message 37639.  

Can t wait to see the productization of all those great discoveries.


I imagine it will be a long time before average Joe's can consider owning something like this. We need to buy our way through the current chips so Intel can make as much money as possible off all of this.


That is why we need AMD.

And why we also need Intel.

If there were only one company in the marketplace, it could hold stuff back in exactly the way you suggest.

In a multi-supplier environment (and two counts as multi, just) then there is a race to see who can get to market first. Intel will want to get this out as soon as it can, in case AMD gets something similar out first.

It will be a long time coming, but more because a lot of work is still needed - new ways of compiling code for example (see this week's New Scientist) as well as the more hardware-oriented aspects - how to support this on a motherboard, what to use as a BIOS, wheter we will still offer DOS 16-bit backward compatibility, etc etc.

R~~
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Message 38810 - Posted: 1 Apr 2007, 16:15:50 UTC

Doh!

I was thinking recently about the memory requirements of multi-core processors. I don't know if this has been discussed or not, but if multi-core processors are all the rage in a few years, as it seems they will be, will not the motherboard makers also have to respond with motherboards that have a major increase in memory capacity? Think about it; 8-core or 16-core processors in a few years: how much memory will these hogs have to take to run 8 or 16 cores of BOINC? Or am I missing something basic here? It seems to me that the memory requirements might add substantially to the cost of an upgrade to these CPUs. What's the scoop on future memory for multi-cores?

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Message 38836 - Posted: 2 Apr 2007, 3:19:02 UTC

Maybe 64 gig sticks will come. Motherboards may have to be ten layers deep.
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Message 39057 - Posted: 5 Apr 2007, 19:15:30 UTC

I gotta think that both AMD and Intel are thinking about this and 8 or 16 channel RAM. Quad channel memory is already available on serverboards.

Also, with each die shrink, and I think they can get down to 25nm? The amount of room for on CPU memory cache gets larger (unless they add more processors).
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Message 39302 - Posted: 12 Apr 2007, 12:41:04 UTC - in response to Message 38810.  
Last modified: 12 Apr 2007, 12:42:39 UTC

IBM's chip-stacking could speed data transfers

"IBM has found a way to connect chips inside products ranging from cell phones to supercomputers, an advance that promises to prolong battery life in wireless devices and eventually speed data transfers between the processor and memory chips in computers, the company said Thursday.

The memory and processor chips are often spaced inches apart from each other, causing a lag in transmission as chipmakers multiply the number and voracity of calculating cores on their processors.

Slowdowns crop up when data-hungry processors cannot retrieve information fast enough from memory to perform their increasingly complex functions.

In IBM’s solution, two chips are sandwiched on top of one another — the distance between them measured in microns, or millionths of a meter — and held together by vertical connections that are etched in silicon holes that are filled with metal.

The company said it could have memory-on-processor technology by 2009 for use in servers, supercomputers and other machines."



I was thinking recently about the memory requirements of multi-core processors.

Or am I missing something basic here?

What's the scoop on future memory for multi-cores?

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Message 39319 - Posted: 12 Apr 2007, 19:05:12 UTC

have you seen this yet????????....http://www.ipodobserver.com/story/31058
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Message 39323 - Posted: 12 Apr 2007, 21:32:04 UTC - in response to Message 39319.  

'tis interesting, thanx for sharing...

Scientific Computing on the Apple TV

The Pentium M processor in the Apple TV packs a 2.4 gigaflop punch for not a lot of money and a fraction of the power and space of a Mac Mini, according to the My Mac & Apple TV Blog.

That naturally leads to the idea of using the Apple TV as a component in a distributed processing system for scientific research.

"The Apple TV now joins the PS3 as being the second "console" type unit to participate in online grid science. Sony’s game console’s participation in Stanford University’s Folding@Home project has been nothing less than stellar, however it has been stated that the kinds of grid-computing calculations that the PS3’s Cell processor can be used for are fairly limited," the Blogsite reported.

On the other hand, the Intel CPU and Mac OS X offer the possibility of an inexpensive general purpose grid computer. "Having deployed the first Apple TV for grid computing purposes, I have been folding proteins for Rosetta@Home using the BOINC client for two days now with great success."

have you seen this yet????????....http://www.ipodobserver.com/story/31058

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Message boards : Number crunching : 80 cores, not science fiction ... it is real! 1.2 TERA!



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