Message boards : Number crunching : Cpu L2/L3 cache
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[VENETO] boboviz Send message Joined: 1 Dec 05 Posts: 1994 Credit: 9,543,381 RAC: 5,926 |
We know that, for Rosetta, the cpu cache (both L2 and L3) is important. So, this cpu may be a monster :-P |
Grant (SSSF) Send message Joined: 28 Mar 20 Posts: 1675 Credit: 17,697,137 RAC: 20,072 |
We know that, for Rosetta, the cpu cache (both L2 and L3) is important.Actually, we know that isn't true when it comes to current CPUs. Due to the size of Rosetta's dataset CPUs with large L2 & L3 caches don't have any significant performance advantage over those with smaller caches. There may be an advantage with those extremely large caches, but then the increased latency may offset that. As it is, the only things that have shown a benefit from extremely large L2/L3 caches have been games, and compression/decompression workloads. The benefits for all other types of work (including compute work) are minimal to non-existent with current CPU architectures. The present caches in the current products are pretty much the optimal size for the current architectures & current core/thread counts for the huge majority of workloads. Of course if you're primarily in to games, or compressing & decompressing files then there would be a benefit to such a CPU (from 4% which is next to nothing, up to 25% which is very significant). For every other purpose, you'd be better of spending the extra money on more cores/threads/ higher IPC etc unless they make some very significant architectural changes that will make use of the much larger caches with current software. Grant Darwin NT |
[VENETO] boboviz Send message Joined: 1 Dec 05 Posts: 1994 Credit: 9,543,381 RAC: 5,926 |
There may be an advantage with those extremely large caches, but then the increased latency may offset that. Rosetta starts to work with virtual machine. So, yes, cpu cache is important. :-) P.S. I know that a lot of cache is better with project based on FFT, but this cpu is litterary a dream for crunchers |
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Number crunching :
Cpu L2/L3 cache
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